Datasheet

Figure 28-3. Enable synchronization busy operation
ENABLE
CK
SYNCBUSY.ENABLE
CLK_APB_OSCCTRL
The frequency of the DPLLCn output clock CLK_DPLLn is stable when the module is enabled and when
the LOCK bit is set. When DPLLnCTRLB.LTIME is different from 0, a user defined lock time is used to
validate the lock operation. In that case the lock time is constant. If DPLLnCTRLB.LTIME is zero, the lock
signal is linked with the status bit of the DPLLCn (DPLLnSTATUS.LOCK), the lock time vary depending
on the filter selection and final target frequency. When DPLLnCTRLB.WUF is set the wake up fast mode
is activated. In that mode the clock gating cell is enabled at the end of the startup time. At that time the
final frequency is not stable as it is still the acquisition period, but it allows to save hundreds of
microseconds. After the first acquisition, DPLLnCTRLB.LBYPASS indicates if the Lock signal is discarded
from the control of the clock gater (CG) generating the output clock CLK_DPLLn.
Table 28-3. CLK_DPLLn behavior from startup to first edge detection.
WUF LTIME CLK_DPLLn Behavior
0 0 Normal Mode: First Edge when
lock is asserted
0 Not Equal To Zero Lock Timer Timeout mode: First
Edge when the timer down-
counts to 0.
1 X Wake Up Fast Mode: First Edge
when CK is active (startup time)
Table 28-4. CLK_DPLLn behavior after First Edge detection.
LBYPASS CLK_DPLLn Behavior
0 Normal Mode: the CLK_DPLLn is turned off when
lock signal is low.
1 Lock Bypass Mode: the CLK_DPLLn is always
running, lock is irrelevant.
Figure 28-4. CK and CLK_DPLL output from DPLL off mode to running mode
CKR
ENABLE
CK
LOCK
CK STABLEtstartup_time tlock_time
CLK_DPLL
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 774