Datasheet

• XOSC0 and XOSC1: These clocks are provided by the External Multipurpose Crystal Oscillator
(XOSC).
• GCLK: This clock is provided by the Generic Clock Controller.
When the controller is enabled, the relationship between the reference clock frequency and the output
clock frequency is as shown below:

CLK_DPLLn
= 
CKR
× LDR + 1 +
LDRFRAC
32
Where:
f
CLK_DPLLn
is the frequency of the DPLL output clock, LDR is the loop divider ratio integer part and
LDRFRAC is the loop divider ratio fractional part, f
CKR
is the frequency of the selected reference clock.
Figure 28-2. DPLL Block Diagram
XIN
XOUT
XOSCn
XIN32
XOUT32
XOSC32K
GCLK_DPLL
DIVIDER
DPLLCTRLB.DIV
DPLLCTRLB.REFCLK
DIGITAL FILTER
TDC
DPLLCTRLB.FILTER
DCO
CLK_DPLL
RATIO
DPLLRATIO
CK
CKR
CG
When the controller is disabled, the output clock is low. If the Loop Divider Ratio Fractional part bit field in
the DPLL Ratio register (DPLLRATIO.LDRFRAC) is zero, the DPLL works in Integer mode. Otherwise,
the fractional mode is activated. The fractional part has a negative impact on the jitter of the DPLL.
For example (Integer mode only): Assuming f
CKR
= 32 kHz and f
CLK_DPLLn
= 112 MHz, the
multiplication ratio is 3500. It means that LDR must be set to 3499.
For example (Fractional mode): Assuming f
CKR
= 32 kHz and f
CLK_DPPLn
= 112.003000
MHz, the multiplication ratio is 3500.9375 (3500 + 3/32). Thus LDR is set to 3499 and
LDRFRAC to 3.
Related Links
14. GCLK - Generic Clock Controller
29. OSC32KCTRL – 32KHz Oscillators Controller
28.6.5.1 Basic Operation
Initialization, Enabling, Disabling, and Resetting
The DPLLCn is enabled by writing a ‘1’ to the Enable bit in the Control register (DPLLnCTRLA.ENABLE).
The DPLLCn is disabled by writing a ‘0’ to DPLLnCTRLA.ENABLE. The DPLLnSYNCBUSY.ENABLE is
set when the DPLLnCTRLA.ENABLE bit is modified. It is cleared when the DPLLCn output clock
CLK_DPLLn has sampled the bit at the high level, or cleared when the output clock is no longer running
(for disable operation).
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 773