Datasheet

USB Clock Recovery Mode
USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame
(SOF). This mode is enabled by writing a '1' to both the USB Clock Recovery Mode bit and the Mode bit
in DFLL Control register (DFLLCTRLB.USBCRM and DFLLCTRLB.MODE).
In USB Clock Recovery mode, the status bits of the DFLL in OSCCTRL.STATUS are determined by the
USB bus activity, and have no valid meaning. The SOF signal from USB device will be used as reference
clock (CLK_DFLL_REF), ignoring the selected generic clock reference. When the USB device is
connected, a SOF will be sent every 1ms, thus DFLLVAL.MUX bits should be written to 0xBB80 to obtain
a 48MHz clock. In USB clock recovery mode, the DFLLCTRLB.BPLCKC bit state is ignored, and the
value stored in the DFLLVAL.COARSE will be used as final Coarse value.
The COARSE value for a calibrated 48 MHz frequency is loaded from NVM after any system reset and
may vary in operating modes different of the USB Clock Recovery Mode. The initial COARSE value can
be saved and restored by the software if necessary.
The locking procedure will also go instantaneously to the fine lock search.
The DFLLCTRLB.QLDIS bit must be cleared and DFLLCTRLB.CCDIS should be set to speed up the lock
phase. The DFLLCTRLB.STABLE bit state is ignored, an auto jitter reduction mechanism is used instead.
Wake from Sleep Modes
DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After
Wake bit (DFLLCTRLB.LLAW) in the DFLL Control register. If DFLLCTRLB.LLAW is zero, the DFLL48M
will be re-enabled and start running with the same configuration as before being disabled, even if the
reference clock is not available. The locks will not be lost. Thus it is important that the user checks that
the DFLL48M has reached the COARSE and FINE lock stage before entering a sleep mode. When the
reference clock has restarted, the Fine tracking will quickly compensate for any frequency drift during
sleep if DFLLCTRLB.STABLE is zero. If DFLLCTRLB.LLAW is one when disabling the DFLL48M, the
DFLL48M will lose all its locks, and needs to regain these through the full lock sequence.
Wait for Lock
DFLL48M can optionally control the issued clock. This is configured by the Wait For Lock bit
(DFLLCTRLB.WAITLOCK) in the DFLL Control register. If DFLLCTRLB.WAITLOCK is zero, the
DFLL48M will issue a clock immediately after the ready bit (STATUS.DFLLRDY) has risen. If
DFLLCTRLB.WAITLOCK is one, the DFLL48M will issue a clock immediately after the fine lock bit
(STATUS.DFLLCKF) has risen. Using the wait for lock feature allows a better accuracy of the issued
DFLL48M clock, conversely it increases the startup time of the DFLL48M clock.
Accuracy
There are two main factors that determine the accuracy of Fclkdfll48m. These can be tuned to obtain
maximum accuracy when fine lock is achieved.
• Fine resolution: The frequency step between two Fine values.
• The accuracy of the reference clock.
28.6.5 Digital Phase Locked Loop (DPLL) Operation
The task of the DPLL is to maintain coherence between the input (reference) signal and the respective
output frequency CLK_DPLL through phase comparison. The DPLL controller supports four independent
sources of reference clocks:
• XOSC32K: This clock is provided by the 32K External Crystal Oscillator (XOSC32K).
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 772