Datasheet

stored in the DFLL Multiplication Ratio Difference bit group (DFLLVAL.DIFF) in the DFLL Value register.
The relative error on CLK_DFLL48M compared to the target frequency is calculated as follows:
ERROR =
DIFF
MUL
Drift Compensation
If the Stable DFLL Frequency bit (DFLLCTRLB.STABLE) in the DFLL Control register is zero, the
frequency tuner will automatically compensate for drift in the CLK_DFLL48M without losing either of the
locks. This means that DFLLVAL.FINE can change after every measurement of CLK_DFLL48M. If the
DFLLVAL.FINE value overflows or underflows due to large drift in temperature and/or voltage, the DFLL
Out Of Bounds bit (STATUS.DFLLOOB) in the Status register will be set. After an Out of Bounds error
condition, the user must rewrite DFLLMUL.MUL to ensure correct CLK_DFLL48M frequency. An interrupt
is generated on a zero-to-one transition on STATUS.DFLLOOB if the DFLL Out Of Bounds bit
(INTENSET.DFLLOOB) in the Interrupt Enable Set register is set. This interrupt will also be set if the tuner
is not able to lock on the correct Coarse value. If the Stable DFLL Frequency bit (DFLLCTRLB.STABLE)
in the DFLL Control register is one, the DFLLVAL.COARSE and DFLLVAL.FINE values will stay constant
after the lock. The user can check for a possible drift by reading the frequency error in the DFLL
Multiplication Ratio Difference bit group (DFLLVAL.DIFF).
Reference Clock Stop Detection
If CLK_DFLL48M_REF stops or is running at a very low frequency (slower than CLK_DFLL48M/(2 *
MULMAX)), the DFLL Reference Clock Stopped bit (STATUS.DFLLRCS) in the Status register will be set.
Detecting a stopped reference clock can take a long time, on the order of 2
17
CLK_DFLL48M cycles.
When the reference clock is stopped, the DFLL48M will operate as if in open-loop mode. Closed-loop
mode operation will automatically resume if the CLK_DFLL48M_REF is restarted. An interrupt is
generated on a zero-to-one transition on STATUS.DFLLRCS if the DFLL Reference Clock Stopped bit
(INTENSET.DFLLRCS) in the Interrupt Enable Set register is set.
Related Links
9.4 NVM User Page Mapping
14. GCLK - Generic Clock Controller
28.6.4.2 Additional Features
Dealing with Delay in the DFLL in Closed-Loop Mode
The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M
can be up to several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in
the DFLL48M locking mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a
chill cycle, during which the CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is
enabled by default, but can be disabled by writing a one to the DFLL Chill Cycle Disable bit
(DFLLCTRLB.CCDIS) in the DFLL Control register. Enabling chill cycles might double the lock time.
Another solution to this problem consists of using less strict lock requirements. This is called Quick Lock
(QL), which is also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable
bit (DFLLCTRLB.QLDIS) in the DFLL Control register. The Quick Lock might lead to a larger spread in the
output frequency than chill cycles, but the average output frequency is the same.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 771