Datasheet

1. Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock
Channel 0 (DFLL48M_Reference). Refer to GCLK for details.
2. Select the maximum step size allowed in finding the Coarse and Fine values by writing the
appropriate values to the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups
(DFLLMUL.CSTEP and DFLLMUL. FSTEP) in the DFLL Multiplier register. A small step size will
ensure low overshoot on the output frequency, but will typically result in longer lock times. A high
value might give a large overshoot, but will typically provide faster locking. DFLLMUL.CSTEP and
DFLLMUL.FSTEP should not be higher than 50% of the maximum value of DFLLVAL.COARSE and
DFLLVAL.FINE, respectively.
3. Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL
Multiplier register. Care must be taken when choosing DFLLMUL.MUL so that the output frequency
does not exceed the maximum frequency of the device. If the target frequency is below the
minimum frequency of the DFLL48M, the output frequency will be equal to the DFLL minimum
frequency.
4. Start the closed loop mode by writing a one to the DFLL Mode Selection bit (DFLLCTRLA.MODE)
in the DFLL Control register.
The frequency of CLK_DFLL48M (Fclkdfll48m) is given by:

clkdfll48m
= DFLLMUL.MUL × 
clkdfll48mref
where Fclkdfll48mref is the frequency of the reference clock (CLK_DFLL48M_REF). DFLLVAL.COARSE
and DFLLVAL.FINE are read-only in closed-loop mode, and are controlled by the frequency tuner to meet
user specified frequency. In closed-loop mode, the value in DFLLVAL.COARSE is used by the frequency
tuner as a starting point for Coarse. Writing DFLLVAL.COARSE to a value close to the final value before
entering closed-loop mode will reduce the time needed to get a lock on Coarse.
Frequency Locking
The locking of the frequency in closed-loop mode is divided into two stages. In the first, coarse stage, the
control logic quickly finds the correct value for DFLLVAL.COARSE and sets the output frequency to a
value close to the correct frequency. On coarse lock, the DFLL Locked on Coarse Value bit
(STATUS.DFLLLOCKC) in the Status register will be set.
In the second, fine stage, the control logic tunes the value in DFLLVAL.FINE so that the output frequency
is very close to the desired frequency. On fine lock, the DFLL Locked on Fine Value bit
(STATUS.DFLLLOCKF) in the Status register will be set.
If the the ByPass Lock bit (DFLLCTRLB.BPLCKC) in the DFLL Control register is set, the coarse stage is
by-passed, the DFLLVAL.COARSE keeps it’s value and the DFLL Coarse Value bit
(STATUS.DFLLLOCKC) is immediately set.
Interrupts are generated by both STATUS.DFLLLOCKC and STATUS.DFLLLOCKF if
INTENSET.DFLLOCKC or INTENSET.DFLLOCKF are written to '1'.
CLK_DFLL48M is ready to be used when the DFLL Ready bit (STATUS.DFLLRDY) in the Status register
is set, but the accuracy of the output frequency depends on which locks are set. For lock times, refer to
the Electrical Characteristics.
Frequency Error Measurement
The ratio between CLK_DFLL48M_REF and CLK48M_DFLL is measured automatically when the
DFLL48M is in closed loop mode. The difference between this ratio and the value in DFLLMUL.MUL is
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 770