Datasheet

10.3 High-Speed Bus System
10.3.1 Features
High-Speed Bus Matrix has the following features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• 32-bit data bus
• Operation at a one-to-one clock frequency with the bus masters
FlexRAM Memory has the following features:
• Unified System Memory area
• Allows concurrent accesses from different masters
• Offers privileged accesses from specific masters
10.3.2 Configuration
Figure 10-1. Master-Slave Relations High-Speed Bus Matrix
High-Speed Bus SLAVES
NVMCTRL0
0
NVMCTRL1
1
SEEPROM
2
SRAM0
3
SRAM1
4
SRAM2
5
SRAM3
6
HSB-PB Bridge A
7
HSB-PB Bridge B
8
HSB-PB Bridge C
9
HSB-PB Bridge D
10
PUKCC
11
SDHC0
12
SDHC1
13
QSPI
14
BACKUPRAM
15
High-Speed Bus
MASTERS
CM4S 0
CMCC 1
DMAC DTWR 4
DMAC DTRD 5
ICM 6
DSU 7
Table 10-1. High Speed Bus Matrix Masters
High-Speed Bus Matrix Masters Master ID
CM4S - Cortex M4 Processor 0
CMCC - Cortex-M Cache Controller 1
DMAC - Direct Memory Access Controller / Data
Write Access
4
DMAC - Direct Memory Access Controller / Data
Read Access
5
SAM D5x/E5x Family Data Sheet
Processor and Architecture
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 77