Datasheet

28.6.4.1 Basic Operation
Operating modes
The DFLL48M will behave differently in different sleep modes based on the settings of
DFLLCTRLA.RUNSTDBY, DFLLCTRLA.ONDEMAND and DFLLCTRLA.ENABLE, as shown in the
following table.
Table 28-2. DFLL48M Sleep Behavior
DFLLCTRLA.RUNSTD
BY
DFLLCTRLA.ONDEMA
ND
DFLLCTRLA.ENABLE Sleep Behavior
- - 0 Disabled
0 0 1 Always run in Idle Sleep
modes. Run in Standby
Sleep mode if requested
by a peripheral.
0 1 1 Only run in Idle or
Standby Sleep modes if
requested by a
peripheral.
1 0 1 Always run in Idle and
Standby Sleep modes.
1 1 1 Only run in Idle or
Standby Sleep modes if
requested by a
peripheral.
The DFLL48M is used as a clock source for the generic clock generators, as described in the GCLK
chapter.
The DFLL48M is factory-calibrated for 48MHz. Registers DFLLVAL.COARSE and DFLLVAL.FINE store
frequency calibration after reset.
Open-Loop Operation
After any reset, the open-loop mode is selected. When operating in open-loop mode, the output
frequency of the DFLL48M will be determined by the values written to the DFLL Coarse Value bit group
and the DFLL Fine Value bit group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register.
It is possible to change the values of DFLLVAL.COARSE and DFLLVAL.FINE and thereby the output
frequency of the DFLL48M output clock, CLK_DFLL48M, while the DFLL48M is enabled and in use.
CLK_DFLL48M is ready to be used when STATUS.DFLLRDY is set after enabling the DFLL48M.
Closed-Loop Operation
In closed-loop operation, the output frequency is continuously regulated against a reference clock. Once
the multiplication factor is set, the oscillator fine tuning is automatically adjusted. The DFLL48M must be
correctly configured before closed-loop operation can be enabled. After enabling the DFLL48M, it must
be configured in the following way:
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 769