Datasheet

(INTFLAG.CLKFAILn) is set. If the CLKFAILn bit in the Interrupt Enable Set register
(INTENSET.CLKFAILn) is set, an interrupt is generated . An output event is generated as well, if the
Event Output enable bit in the Event Control register (EVCTRL.CFDEOn) is set.
The XOSCn clock continues to be monitored after a clock failure. The Clock Failure status bit in the
Status register (STATUS.CLKFAILn) reflects the current XOSCn clock activity.
Clock Switch
When a clock failure is detected, the XOSCn clock is replaced by the safe clock in order to maintain an
active clock during the XOSCn clock failure. The safe clock source is the DFLL48M oscillator clock. The
safe clock source can be downscaled with a configurable prescaler to ensure that the safe clock
frequency does not exceed the operating conditions selected by the application. When the XOSCn clock
is switched to the safe clock, the Clock Switch bit (STATUS.CLKSWn) in the Status register is set.
When the CFD has switched to the safe clock, the XOSCn is not disabled. The application must take the
necessary actions to disable the oscillator N. The application must also take the necessary actions to
configure the system clocks to continue normal operations.
In the case the application can recover the XOSCn , it can switch back to the XOSCn clock by writing a
one to Switch Back bit (XOSCCTRLn.SWBCK) in the External Oscillator Control register. Once the
XOSCn clock is switched back, the Switch Back bit (XOSCCTRLn.SWBCK) is cleared by the hardware.
Prescaler
The CFD has an internal configurable prescaler (XOSCCTRLn.CFDPRESC) to generate the safe clock
from the DFLL48M clock. The prescaler size allows to scale down the DFLL48M clock such that the safe
clock is not higher than the XOSCn clock frequency monitored by the CFD. The frequency divider is
2^CFDPRESC where CFDPRESC range from 0 to 15.
Example: for an external crystal oscillator at 8 mHz and the DFLL48M internal oscillator configured to
generate a 48 mHz clock, the prescaler should select a downscale value above 6 (48/8), eg. 8, thus
CFDPRESC=3.
Event
If the Event Output enable bit in the Event Control register (EVCTRL.CFDEOn) is set, the CFD clock
failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock
failure will not be output on the Event Output.
Sleep Mode
The CFD is halted depending on configuration of the XOSCn and the peripheral clock request. For further
details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device
from sleep modes.
28.6.4 Digital Frequency Locked Loop (DFLL48M) Operation
The DFLL48M can operate in both open-loop mode and closed-loop mode. In closed-loop mode, a low-
frequency clock with high accuracy should be used as the reference clock to get high accuracy on the
output clock (CLK_DFLL48M).
The DFLL48M can be used as a source for the generic clock generators.
Related Links
14. GCLK - Generic Clock Controller
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 768