Datasheet

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XOSCCTRLn.RUNS
TDBY
XOSCCTRLn.ONDE
MAND
XOSCTRLn.ENABL
E
Sleep Behavior
1 0 1 Always run in Idle and Standby
Sleep modes.
1 1 1 Only run in Idle or Standby Sleep
modes if requested by a
peripheral.
After a hard reset, or when waking up from a sleep mode where the XOSCn was disabled, the XOSCn
will need a certain amount of time to stabilize on the correct frequency. This start-up time can be
configured by changing the Oscillator Start-Up Time bit group (XOSCCTRLn.STARTUP) in the External
Multipurpose Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to
ensure that no unstable clock propagates to the digital logic. The External Multipurpose Crystal Oscillator
Ready bit in the Status register (STATUS.XOSCRDYn) is set when the external clock or crystal oscillator
is stable and ready to be used as a clock source. An interrupt is generated on a zero-to-one transition on
STATUS.XOSCRDYn if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set
register (INTENSET.XOSCRDYn) is set.
Related Links
14. GCLK - Generic Clock Controller
28.6.3 Clock Failure Detection Operation
The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator clock
signal provided by the External Multipurpose Crystal Oscillator (XOSCn). It detects failing operation of the
XOSCn clock, and allows to switch to a safe clock in case of clock failure. The user can also switch from
the safe clock to the XOSCn clock in case of clock recovery. The safe clock is derived from the DFLL48M
with a configurable prescaler. This allows to configure the safe clock in order to fulfill the operative
conditions of the microcontroller. The CFD operation is automatically suspended when the XOSCn clock
is not requested in ONDEMAND mode or halted in STANDBY.
The user interface registers allow to enable, disable and configure the CFD. The Status register gives
status on failure and clock switch conditions. The Clock Failure Detector can optionally trigger an interrupt
or an event when a failure is detected.
Clock Failure Detection
At reset, the CFD is disabled. The CFD does not monitor the XOSCn clock when the oscillator is disabled
(XOSCCTRLn.ENABLE = 0).
Before starting the CFD operation, the user must start and enable the safe clock source (DFLL48M). To
start the CFD operation, the user must write a one to the CFD Enable bit in the External Oscillator Control
register (XOSCCTRLn.CFDEN). After the start or restart of the XOSCn, the CFD does not detect failure
until the start-up time, as configured by the Oscillator Start-Up Time (XOSCCTRLn.STARTUP) in the
External Multipurpose Crystal Oscillator Control register, is elapsed. Once the XOSCn Start-Up Time is
elapsed, the XOSCn clock is constantly monitored.
During a period of 4 safe clocks , the CFD watches for a clock activity from the XOSCn. There must be
one rising and one falling XOSCn clock edges during a 4 safe clock periods to meet a non failure status.
If no activity is detected, the failure status is asserted. The Clock Failure status bit in the Status register
(STATUS.CLKFAILn) is set. The Clock Failure interrupt flag bit in the Interrupt Flag register
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 767