Datasheet

The DFLL48M requires a reference clock (GCLK_DFLL48M_REF) from the GCLK. The control logic uses
the oscillator output, which is also asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due
to this asynchronicity, writes to certain registers will require synchronization between the clock domains.
Refer to Synchronization for further details.
The FDPLL200Mn require a reference clock (GCLK_DPLL) for the FDPLL output. When the optional lock
timer timeout function is used, a 32KHz reference clock (GCLK_DPLL_32K) is also required. Both
reference clocks can either stem from the GCLK and/or from external oscillators.
28.5.4 DMA
Not applicable.
28.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the OSCCTRL interrupts requires
the interrupt controller to be configured first.
Related Links
10.2 Nested Vector Interrupt Controller
28.5.6 Events
The events of this peripheral are connected to the Event System.
Related Links
31. EVSYS – Event System
28.5.7 Debug Operation
When the CPU is halted in debug mode the OSCCTRL continues normal operation. If the OSCCTRL is
configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar,
improper operation or data loss may result during debugging.
28.5.8 Register Access Protection
All registers with write access can be write-protected optionally by the Peripheral Access Controller
(PAC), except for the following registers:
• Interrupt Flag Status and Clear register (INTFLAG)
Note: Optional write protection is indicated by the "PAC Write Protection" property in the register
description.
Write protection does not apply for accesses through an external debugger.
28.5.9 Analog Connections
The 8-48 MHz crystal must be connected between the XIN and XOUT pins, along with any required load
capacitors.
Note: Refer to the Electrical Characteristics for more information about load capacitors.
28.6 Functional Description
28.6.1 Principle of Operation
XOSC, DFLL48M, and DPLL200M are configured via OSCCTRL control registers. Through this interface,
the oscillators are enabled, disabled, or have their calibration values updated.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 765