Datasheet

28.3 Block Diagram
Figure 28-1. OSCCTRL Block Diagram
OSCILLATORS
CONTROL
STATUS
INTERRUPTS
GENERATOR
Interrupts
OSCCTRL
XIN[1:0]XOUT[1:0]
CLK_XOSC1
CLK_DFLL48M
CLK_DPLL1
CFD Event1
CLK_DPLL0
CFD Event0
CLK_XOSC0
2 2
FDPLL200M
FDPLL200M
DFLL48M
XOSC
XOSC
CFD
CFD
28.4 Signal Description
Signal Description Type
XIN[1:0] Multipurpose Crystal Oscillator or external clock generator input Analog input
XOUT[1:0] Multipurpose Crystal Oscillator output Analog output
The I/O lines are automatically selected when XOSCn is enabled.
28.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
28.5.1 I/O Lines
I/O lines are configured by OSCCTRL when XOSCn is enabled, and need no user configuration.
28.5.2 Power Management
The OSCCTRL can continue to operate in any sleep mode where the selected source clock is running.
The OSCCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger
other operations in the system without exiting sleep modes.
Related Links
18. PM – Power Manager
28.5.3 Clocks
The OSCCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock
Controller (GCLK). The available clock sources are: XOSCn, DFLL48M, and FDPLL200Mn.
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 764