Datasheet

28. OSCCTRL – Oscillators Controller
28.1 Overview
The Oscillators Controller (OSCCTRL) provides a user interface to the XOSCn, DFLL48M, and two
FDPLL200M.
Through the interface registers, it is possible to enable, disable, calibrate, and monitor the oscillators.
The status of all oscillators are collected in the Status register (STATUS). They can additionally trigger
interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers.
28.2 Features
• Digital Frequency-Locked Loop (DFLL48M)
– Internal oscillator with no external components
– 48 MHz output frequency
– Operates stand-alone as a high-frequency programmable oscillator in Open Loop mode
– Operates as an accurate frequency multiplier against a known frequency in Closed Loop mode
• Two 8-48 MHz Crystal Oscillators (XOSCn)
– Tunable gain control
– Programmable start-up time
– Crystal or external input clock on XIN I/O
– Clock failure detection with safe clock switch
– Clock failure event output
• Two Digital Phase-Locked Loop (DPLLn)
– 96 MHz to 200 MHz output frequency from a 32 kHz to 3.2 MHz reference clock
– Two DPLLs, each with four selectable reference clocks
– Adjustable digital filter for jitter optimization
– Adjustable DCO filter for a 4-stages differential ring oscillator
– Fractional part used to achieve 1/32th of reference clock step
– Embedded test mode controller
SAM D5x/E5x Family Data Sheet
OSCCTRL – Oscillators Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 763