Datasheet

27.7.8 Peripheral Interrupt Flag Status - Bridge C
Name: INTFLAGC
Offset: 0x1C
Reset: 0x00000000
Property: –
These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated
with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to these bits has no effect.
Writing a '1' to these bits will clear the corresponding INTFLAGx interrupt flag.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CCL QSPI PUKCC ICM TRNG AES
Access
RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PDEC TC5 TC4 TCC3 TCC2 GMAC CAN1 CAN0
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 14 – CCL Interrupt Flag for CCL
This flags is set when a Peripheral Access Error occurs while accessing the peripheral associated with
the CCL, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the CCL interrupt flag.
Bit 13 – QSPI Interrupt Flag for QSPI
This flags is set when a Peripheral Access Error occurs while accessing the peripheral associated with
the QSPI, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the QSPI interrupt flag.
Bit 12 – PUKCC Interrupt Flag for PUKCC
This flags is set when a Peripheral Access Error occurs while accessing the peripheral associated with
the PUKCC, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the PUKCC interrupt flag.
SAM D5x/E5x Family Data Sheet
PAC - Peripheral Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 746