Datasheet

27.7.7 Peripheral Interrupt Flag Status - Bridge B
Name: INTFLAGB
Offset: 0x18
Reset: 0x00000000
Property: –
These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated
with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to these bits has no effect.
Writing a '1' to these bits will clear the corresponding INTFLAGx interrupt flag.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RAMECC
Access
RW
Reset 0
Bit 15 14 13 12 11 10 9 8
TC3 TC2 TCC1 TCC0 SERCOM3 SERCOM2
Access
RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EVSYS DMAC PORT CMCC NVMCTRL DSU USB
Access
RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0
Bit 16 – RAMECC Interrupt Flag for RAMECC
This flag is set when a Peripheral Access Error occurs while accessing the RAMECC, and will generate
an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the RAMECC interrupt flag.
Bit 14 – TC3 Interrupt Flag for TC3
This flag is set when a Peripheral Access Error occurs while accessing the TC3, and will generate an
interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the TC3 interrupt flag.
Bit 13 – TC2 Interrupt Flag for TC2
This flag is set when a Peripheral Access Error occurs while accessing the TC2, and will generate an
interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the TC2 interrupt flag.
SAM D5x/E5x Family Data Sheet
PAC - Peripheral Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 743