Datasheet

27.7.6 Peripheral Interrupt Flag Status - Bridge A
Name: INTFLAGA
Offset: 0x14
Reset: 0x00000000
Property: –
These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated
with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to these bits has no effect.
Writing a '1' to these bits will clear the corresponding INTFLAGx interrupt flag.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
TC1 TC0 SERCOM1 SERCOM0 FREQM EIC RTC WDT
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 – TC1 Interrupt Flag for TC1
This bit is set when a Peripheral Access Error occurs while accessing the TC1, and will generate an
interrupt request if SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the flag.
Bit 14 – TC0 Interrupt Flag for TC0
This bit is set when a Peripheral Access Error occurs while accessing the TC0, and will generate an
interrupt request if SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the flag.
Bit 13 – SERCOM1 Interrupt Flag for SERCOM1
This bit is set when a Peripheral Access Error occurs while accessing the SERCOM1, and will generate
an interrupt request if SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the flag.
SAM D5x/E5x Family Data Sheet
PAC - Peripheral Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 740