Datasheet

27.7.5 Bridge Interrupt Flag Status
Name: INTFLAGAHB
Offset: 0x10
Reset: 0x00000000
Property: -
These flags are cleared by writing a '1' to the corresponding bit.
These flags are set when an access error is detected by the corresponding AHB slave, and will generate
an interrupt request if INTENCLR/SET.ERR is '1'.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
QSPI SDHC1 SDHC0 PUKCC HPB3 HPB2 HPB1
Access
RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
HPB0 RAMDMACICM RAMDMAWR RAMPPPDSU RAMCM4S NVMCTRL2 NVMCTRL1 NVMCTRL0
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 14 – QSPI Interrupt Flag for QSPI
This flag is set when an access error is detected by the QSPI AHB slave, and will generate an interrupt
request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the QSPI interrupt flag.
Bit 13 – SDHC1 Interrupt Flag for SDHC1
This flag is set when an access error is detected by the SDHC1 AHB slave, and will generate an interrupt
request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the SDHC1 interrupt flag.
Bit 12 – SDHC0 Interrupt Flag for SDHC0
This flag is set when an access error is detected by the SDHC0 AHB slave, and will generate an interrupt
request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the SDHC0 interrupt flag.
SAM D5x/E5x Family Data Sheet
PAC - Peripheral Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 737