Datasheet

Table Of Contents

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Offset Name Bit Pos.

0x38 STATUSB

7:0 EVSYS DMAC PORT CMCC NVMCTRL DSU USB

15:8 TC3 TC2 TCC1 TCC0 SERCOM3 SERCOM2

23:16 RAMECC

31:24

0x3C STATUSC

7:0 PDEC TC5 TC4 TCC3 TCC2 GMAC CAN1 CAN0

15:8 CCL QSPI PUKCC ICM TRNG AES AC

23:16

31:24

0x40 STATUSD

7:0 ADC0 TC7 TC6 TCC4 SERCOM7 SERCOM6 SERCOM5 SERCOM4

15:8 PCC I2S DAC ADC1

23:16

31:24

27.7 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the

8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be

accessed directly.

Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC

write protection is denoted by the "PAC Write-Protection" property in each individual register description.

For details, refer to the related links.