Datasheet

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs. Each
interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set
(INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear
(INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the
corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared,
the interrupt is disabled, or the PAC is reset. All interrupt requests from the peripheral are ORed together
on system level to generate one combined interrupt request to the NVIC. The user must read the
INTFLAGAHB and INTFLAGn registers to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
Related Links
10.2 Nested Vector Interrupt Controller
27.5.5 Events
The PAC can generate the following output event:
• Error (ERR): Generated when one of the interrupt flag registers bits is set
Writing a '1' to an Event Output bit in the Event Control Register (EVCTRL.ERREO) enables the
corresponding output event. Writing a '0' to this bit disables the corresponding output event.
27.5.6 Sleep Mode Operation
In Sleep mode, the PAC is kept enabled if an available bus master (CPU, DMA) is running. The PAC will
continue to catch access errors from the module and generate interrupts or events.
27.5.7 Synchronization
Not applicable.
SAM D5x/E5x Family Data Sheet
PAC - Peripheral Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 729