Datasheet

value that defines the operation to be done on the control access bit. These operations can be “clear
protection”, “set protection” and “set and lock protection bit”.
The “clear protection” operation will remove the write access protection for the peripheral selected by
WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral.
The “set protection” operation will set the write access protection for the peripheral selected by
WRCTRL.PERID. Write accesses are not allowed for the registers with write protection property in this
peripheral.
The “set and lock protection” operation will set the write access protection for the peripheral selected by
WRCTRL.PERID and locks the access rights of the selected peripheral registers. The write access
protection will only be cleared by a hardware reset.
The peripheral access control status can be read from the corresponding STATUSn register.
27.5.2.5 Write Access Protection Management Errors
Only word-wise writes to the WRCTRL register will effectively change the access protection. Other type of
accesses will have no effect and will cause a PAC write access error. This error is reported in the
INTFLAGn.PAC bit corresponding to the PAC module.
PAC also offers an additional safety feature for correct program execution with an interrupt generated on
double write clear protection or double write set protection. If a peripheral is write protected and a
subsequent set protection operation is detected then the PAC returns an error, and similarly for a double
clear protection operation.
In addition, an error is generated when writing a “set and lock” protection to a write-protected peripheral
or when a write access is done to a locked set protection. This can be used to ensure that the application
follows the intended program flow by always following a write protect with an unprotect and conversely.
However in applications where a write protected peripheral is used in several contexts, e.g. interrupt, care
should be taken so that either the interrupt can not happen while the main application or other interrupt
levels manipulates the write protection status or when the interrupt handler needs to unprotect the
peripheral based on the current protection status by reading the STATUS register.
The errors generated while accessing the PAC module registers (eg. key error, double protect error...) will
set the INTFLAGn.PAC flag.
27.5.2.6 AHB Slave Bus Errors
The PAC module reports errors occurring at the AHB Slave bus level. These errors are generated when
an access is performed at an address where no slave (bridge or peripheral) is mapped . These errors are
reported in the corresponding bits of the INTFLAGAHB register.
27.5.2.7 Generating Events
The PAC module can also generate an event when any of the Interrupt Flag registers bit are set. To
enable the PAC event generation, the control bit EVCTRL.ERREO must be set a '1'.
27.5.3 DMA Operation
Not applicable.
27.5.4 Interrupts
The PAC has the following interrupt source:
• Error (ERR): Indicates that a peripheral access violation occurred in one of the peripherals controlled
by the PAC module, or a bridge error occurred in one of the bridges reported by the PAC
– This interrupt is a synchronous wake-up source.
SAM D5x/E5x Family Data Sheet
PAC - Peripheral Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 728