Datasheet

Table Of Contents

27.5 Functional Description

27.5.1 Principle of Operation

The Peripheral Access Control module allows the user to set a write protection on peripheral modules

and generate an interrupt in case of a peripheral access violation. The peripheral’s protection can be set,

cleared or locked at the user discretion. A set of Interrupt Flag and Status registers informs the user on

the status of the violation in the peripherals. In addition, slaves bus errors can be also reported in the

cases where reserved area is accessed by the application.

27.5.2 Basic Operation

27.5.2.1 Initialization, Enabling and Resetting

The PAC is always enabled after reset.

Only a hardware reset will reset the PAC module.

27.5.2.2 Operations

The PAC module allows the user to set, clear or lock the write protection status of all peripherals on all

Peripheral Bridges.

If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated

to inform the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n

= A,B,C ...). The corresponding Peripheral Write Control Status n register (STATUSn) gives the state of

the write protection for all peripherals connected to the corresponding Peripheral Bridge n. Refer to

27.5.2.3 Peripheral Access Errors for details.

The PAC module also report the errors occurring at slave bus level when an access to reserved area is

detected. AHB Slave Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the

violation in the corresponding slave. Refer to the 27.5.2.6 AHB Slave Bus Errors for details.

27.5.2.3 Peripheral Access Errors

The following events will generate a Peripheral Access Error:

• Protected write: To avoid unexpected writes to a peripheral's registers, each peripheral can be write

protected. Only the registers denoted as “PAC Write-Protection” in the module’s datasheet can be

protected. If a peripheral is not write protected, write data accesses are performed normally. If a

peripheral is write protected and if a write access is attempted, data will not be written and peripheral

returns an access error. The corresponding interrupt flag bit in the INTFLAGn register will be set.

• Illegal access: Access to an unimplemented register within the module.

• Synchronized write error: For write-synchronized registers an error will be reported if the register is

written while a synchronization is ongoing.

When any of the INTFLAGn registers bit are set, an interrupt will be requested if the PAC interrupt enable

bit is set.