Datasheet

Related Links
18. PM – Power Manager
27.4.3 Clocks
The PAC bus clock (CLK_PAC_APB) can be enabled and disabled in the Main Clock module. The default
state of CLK_PAC_APB can be found in the related links.
Related Links
15. MCLK – Main Clock
15.6.2.6 Peripheral Clock Masking
27.4.4 DMA
Not applicable.
27.4.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the PAC interrupt requires the
Interrupt Controller to be configured first.
Table 27-1. Interrupt Lines
Instances NVIC Line
PAC ERR
Related Links
10.2 Nested Vector Interrupt Controller
27.4.6 Events
The events are connected to the Event System, which may need configuration.
Related Links
31. EVSYS – Event System
27.4.7 Debug Operation
When the CPU is halted in Debug mode, write protection of all peripherals is disabled and the PAC
continues normal operation.
27.4.8 Register Access Protection
All registers with write access can be write-protected optionally by the Peripheral Access Controller
(PAC), except for the following registers:
• Write Control (WRCTRL) register
• AHB Slave Bus Interrupt Flag Status and Clear (INTFLAGAHB) register
• Peripheral Interrupt Flag Status and Clear n (INTFLAG A/B/C...) registers
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write
Protection" property in each individual register description.
PAC write protection does not apply to accesses through an external debugger.
SAM D5x/E5x Family Data Sheet
PAC - Peripheral Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 726