Datasheet

27. PAC - Peripheral Access Controller
27.1 Overview
The Peripheral Access Controller provides an interface for the locking and unlocking of peripheral
registers within the device. It reports all violations that could happen when accessing a peripheral: write
protected access, illegal access, enable protected access, access when clock synchronization or
software reset is on-going. These errors are reported in a unique interrupt flag for a peripheral. The PAC
module also reports errors occurring at the slave bus level, when an access to a non-existing address is
detected.
27.2 Features
• Manages write protection access and reports access errors for the peripheral modules or bridges.
27.3 Block Diagram
Figure 27-1. PAC Block Diagram
INTFLAG
PERIPHERAL m
PERIPHERAL 0
BUSn
BUS0
Peripheral ERROR
Peripheral ERROR
WRITE CONTROL
WRITE CONTROL
PAC CONTROL
PERIPHERAL m
PERIPHERAL 0
SLAVEs
PAC
IRQ
APB
Slave ERROR
27.4 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
27.4.1 IO Lines
Not applicable.
27.4.2 Power Management
The PAC can continue to operate in any Sleep mode where the selected source clock is running. The
PAC interrupts can be used to wake up the device from Sleep modes. The events can trigger other
operations in the system without exiting sleep modes.
SAM D5x/E5x Family Data Sheet
PAC - Peripheral Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 725