Datasheet

26.8.7 Interrupt Status Register
Name: ISR
Offset: 0x1C
Reset: 0x0
Property: Read-Only
Bit 31 30 29 28 27 26 25 24
URAD
Access
R
Reset 0
Bit 23 22 21 20 19 18 17 16
RSU[3:0] REC[3:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RWC[3:0] RBE[3:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RDM[3:0] RHC[3:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 24 – URAD Undefined Register Access Detection Status
The URAD bit is only reset by the SWRST bit in the CTRL register.
The Undefined Register Access Trace bit field in the Undefined Access Status Register (UASR.URAT)
indicates the unspecified access type.
Value Description
0
No undefined register access has been detected since the last SWRST.
1
At least one undefined register access has been detected since the last SWRST.
Bits 23:20 – RSU[3:0] Region Status Updated Detected
RSU[i] is set when a region status updated condition is detected.
Bits 19:16 – REC[3:0] Region End bit Condition Detected
REC[i] is set when an end bit condition is detected.
Bits 15:12 – RWC[3:0] Region Wrap Condition Detected
RWC[i] is set when a wrap condition is detected.
Bits 11:8 – RBE[3:0] Region Bus Error
RBE[i] is set when a bus error is detected while hashing memory region i.
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 717