Datasheet

26.8.6 Interrupt Mask Register
Name: IMR
Offset: 0x18
Reset: 0x00000000
Property: Read-Only
Bit 31 30 29 28 27 26 25 24
URAD
Access
R
Reset 0
Bit 23 22 21 20 19 18 17 16
RSU[3:0] REC[3:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RWC[3:0] RBE[3:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RDM[3:0] RHC[3:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 24 – URAD Undefined Register Access Detection Interrupt Mask
Value Description
0
The interrupt is disabled.
1
The interrupt is enabled.
Bits 23:20 – RSU[3:0] Region Status Updated Interrupt Mask
Value Description
0
When RSU[i] is reading '0', the interrupt is disabled for region i.
1
When RSU[i] is reading '1', the interrupt is enabled for region i.
Bits 19:16 – REC[3:0] Region End bit Condition Detected Interrupt Mask
Value Description
0
When REC[i] is reading '0', the interrupt is disabled for region i.
1
When REC[i] is reading '1', the interrupt is enabled for region i.
Bits 15:12 – RWC[3:0] Region Wrap Condition Detected Interrupt Mask
Value Description
0
When RWC[i] is reading '0', the interrupt is disabled for region i.
1
When RWC[i] is reading '1', the interrupt is enabled for region i.
Bits 11:8 – RBE[3:0] Region Bus Error Interrupt Mask
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 715