Datasheet

Value Description
0
Automatic mode is disabled.
1
When this mode is enabled, the ICM controller automatically switches to active monitoring
after the first Main List pass. Both CDWBN and WBDIS bits have no effect. A '1' must be
written to the End of Monitoring bit in the Region Configuration register (RCFG.EOM) to
terminate the monitoring.
Bits 7:4 – BBC[3:0] Bus Burden Control
This field is used to control the burden of the ICM system bus. The number of system clock cycles
between the end of the current processing and the next block transfer is set to 2
BBC
. Up to 32768 cycles
can be inserted.
Bit 2 – SLBDIS Secondary List Branching Disable
Value Description
0
Branching to the Secondary List is permitted.
1
Branching to the Secondary List is forbidden. The NEXT field of the RNEXT structure
member has no effect and is always considered as zero.
Bit 1 – EOMDIS End of Monitoring Disable
Value Description
0
End of Monitoring is permitted.
1
End of Monitoring is forbidden. The EOM bit of the RCFG structure member has no effect.
Bit 0 – WBDIS Write Back Disable
1:
When the Automatic Switch to Compare Digest bit of this register (CFG.ASCD) is written to '1', this bit
value has no effect.
Value Description
0
Write Back Operations are permitted.
1
Write Back Operations are forbidden: Context register CDWBN bit is internally set to '1' and
cannot be modified by a linked list element. The CDWBN bit of the RCFG structure member
has no effect.
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 707