Datasheet

...........continued
Offset Name Bit Pos.
0x34 HASH
7:0 HASA[0:0]
15:8 HASA[8:1]
23:16 HASA[16:9]
31:24 HASA[24:17]
0x38 UIHVALx0
7:0 VAL[7:0]
15:8 VAL[15:8]
23:16 VAL[23:16]
31:24 VAL[31:24]
0x3C UIHVALx1
7:0 VAL[7:0]
15:8 VAL[15:8]
23:16 VAL[23:16]
31:24 VAL[31:24]
0x40 UIHVALx2
7:0 VAL[7:0]
15:8 VAL[15:8]
23:16 VAL[23:16]
31:24 VAL[31:24]
0x44 UIHVALx3
7:0 VAL[7:0]
15:8 VAL[15:8]
23:16 VAL[23:16]
31:24 VAL[31:24]
0x48 UIHVALx4
7:0 VAL[7:0]
15:8 VAL[15:8]
23:16 VAL[23:16]
31:24 VAL[31:24]
0x4C UIHVALx5
7:0 VAL[7:0]
15:8 VAL[15:8]
23:16 VAL[23:16]
31:24 VAL[31:24]
0x50 UIHVALx6
7:0 VAL[7:0]
15:8 VAL[15:8]
23:16 VAL[23:16]
31:24 VAL[31:24]
0x54 UIHVALx7
7:0 VAL[7:0]
15:8 VAL[15:8]
23:16 VAL[23:16]
31:24 VAL[31:24]
26.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 22.5.8 Register Access Protection.
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 704