Datasheet

• The flag REC[i], i being the region index, is set (if ECIEN is ‘0’) when the hash result is available at
the address defined in HASH.
An interrupt is generated if the bit RHC[i] is written to ‘1’ in the IER (if RHC[i] is set in RCTRL of region i)
or if the bit REC[i] is written to 1 in the IER (if REC[i] is set in RCTRL of region i).
26.6.4.2 Processing Period
The SHA engine processing period can be configured by writing to the Region Configuration Structure
Member register (RCFGn).
The short processing period allows to allocate bandwidth to the SHA module whereas the long
processing period allocates more bandwidth on the system bus to other applications.
In SHA mode, the shortest processing period is 85 clock cycles + 2 clock cycles for start command
synchronization. The longest period is 209 clock cycles + 2 clock cycles.
In SHA256 and SHA224 modes, the shortest processing period is 72 clock cycles + 2 clock cycles for
start command synchronization. The longest period is 194 clock cycles + 2 clock cycles.
26.6.5 ICM Automatic Monitoring Mode
The ASCD bit of the CFG register is used to activate the ICM Automatic Mode. When CFG.ASCD is set,
the ICM performs the following actions:
• The ICM controller passes through the Main List once with CDWBN bit in RCFGn at 0 (i.e., Write
Back activated) and EOM bit in the RCFGn context register at 0.
• When RCFGn.WRAP=1, the ICM controller enters active monitoring, with CDWBN bit in context
register now set, and EOM bit in context register cleared. Writing to the CDWBN and EOM bits in
RCFGn has no effect.
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 700