Datasheet

26.6.3.1.4 Region Next Address Structure Member
Name: RNEXT
Offset: 0x0C + n*0x0C [n=0..3]
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
Access
Reset
26.6.4 Using ICM as an SHA Engine
The ICM can be configured to only calculate a SHA1, SHA224, SHA256 digest value.
26.6.4.1 Settings for Simple SHA Calculation
The start address of the system memory containing the data to hash must be configured in the transfer
descriptor of the DMA embedded in the ICM.
The transfer descriptor is a system memory area integer multiple of 4 x 32-bit word and the start address
of the descriptor must be configured in DSCR (the start address must be aligned on 64-bytes; six LSB
must be cleared). If the data to hash is already padded according to SHA standards, only a single
descriptor is required, and the EOM bit of RCFGn must be written to 1. If the data to hash does not
contain a padding area, it is possible to define the padding area in another system memory location, the
ICM can be configured to automatically jump from a memory area to another one by writing the descriptor
register RNEXT with a value that differs from 0. Writing the RNEXT register with the start address of the
padding area forces the ICM to concatenate both areas, thus providing the SHA result from the start
address of the hash area configured in HASH.
Whether the system memory is configured as a single or multiple data block area, the bits CDWBN and
WRAP must be cleared in the region descriptor structure member RCFGn. The bits WBDIS, EOMDIS,
SLBDIS must be cleared in CFG.
Write the bits RHIEN and ECIEN in the Region Configuration Structure Member (RCFGn) to ‘0’:
• The flag RHC[i], i being the region index, is set (if RHIEN is ‘0’) when the hash result is available at
address defined in HASH.
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 699