Datasheet

Bit 9 – SUIEN Monitoring Status Updated Condition Interrupt Enable
0: The RSU flag is set when the corresponding descriptor is loaded from memory to ICM.
1: The RSU flag remains cleared even if the condition is met.
Bit 8 – ECIEN End Bit Condition Interrupt Enable
0: The REC flag is set when the descriptor having the EOM bit set is processed.
1: The REC flag remains cleared even if the setting condition is met.
Bit 7 – WCIEN Wrap Condition Interrupt Disable
0: The RWC flag is set when the WRAP
1: The RWC flag remains cleared even if the setting condition is met.
Bit 6 – BEIEN Bus Error Interrupt Disable
0: The flag is set when an error is reported on the system bus by the bus MATRIX.
1: The flag remains cleared even if the setting condition is met.
Bit 5 – DMIEN Digest Mismatch Interrupt Disable
0: The RBE flag is set when the hash value just calculated from the processed region dffers from
expected hash value.
1: The RBE flag remains cleared even if the setting condition is met.
Bit 4 – RHIEN Region Hash Completed Interrupt Disable
0: The RHC flag is set when the field NEXT = 0 in a descriptor of the main or second list.
1: The RHC flag remains cleared even if the setting condition is met.
Bit 2 – EOM End of Monitoring
0: The current descriptor does not terminate the monitoring.
1: The current descriptor terminates the Main List. WRAP bit value has no effect.
Bit 1 – WRAP Wrap Command
0: The next region descriptor address loaded is the current region identifier descriptor address
incremented by 0x10.
1: The next region descriptor address loaded is DSCR.
Bit 0 – CDWBN Compare Digest or Write Back Digest
0: The digest is written to the Hash area.
1: The digest value is compared to the digest stored in the Hash area.
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 697