Datasheet

26.6.2 ICM Hash Area
The ICM Hash Area is a contiguous area of system memory that the controller and the processor can
access. The physical location is configured in the ICM hash area start address register. This address is a
multiple of 128 bytes. If the CDWBN bit of the context register is cleared (i.e., Write Back activated), the
ICM controller performs a digest write operation at the following starting location: *(HASH) + (RID<<5),
where RID is the current region context identifier. If the CDWBN bit of the context register is set (i.e.,
Digest Comparison activated), the ICM controller performs a digest read operation at the same address.
26.6.2.1 Message Digest Example
Considering the following 512 bits message (example given in FIPS 180-4):
“61626380000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000018”
The message is written to memory in a Little Endian (LE) system architecture.
Memory Address Address Offset / Byte Lane
0x3 / 31:24 0x2 / 23:16 0x1 / 15:8 0x0 / 7:0
0x000 80 63 62 61
0x004–0x038 00 00 00 00
0x03C 18 00 00 00
The digest is stored at the memory location pointed at by the ICM_HASH pointer with a Region Offset.
Memory Address Address Offset / Byte Lane
0x3 / 31:24 0x2 / 23:16 0x1 / 15:8 0x0 / 7:0
0x000 36 3e 99 a9
0x004 6a 81 06 47
0x008 71 25 3e ba
0x00C 6c c2 50 78
0x010 9d d8 d0 9c
Memory Address Address Offset / Byte Lane
0x3 / 31:24 0x2 / 23:16 0x1 / 15:8 0x0 / 7:0
0x000 22 7d 09 23
0x004 22 d8 05 34
0x008 77 a4 42 86
0x00C b3 55 a2 bd
0x010 e4 bc ad 2a
0x014 f7 b3 a0 bd
0x018 a7 9d 6c e3
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 690