Datasheet

26.5.3 DMA
Not applicable.
26.5.4 Interrupts
The ICM has an interrupt line connected to the Interrupt Controller. Handling the ICM interrupt requires
programming the interrupt controller before configuring the ICM.
Related Links
10.2 Nested Vector Interrupt Controller
26.5.5 Events
Not applicable.
26.5.6 Debug Operation
Not applicable.
26.6 Functional Description
26.6.1 Overview
The Integrity Check Monitor (ICM) is a DMA controller that performs SHA-based memory hashing over
memory regions. As shown in the Block Diagram, it integrates a DMA interface, a Monitoring Finite State
Machine (FSM), an integrity scheduler, a set of context registers, a SHA engine, an interface for
configuration and status registers.
The SHA engine requires a message padded according to FIPS180-4 specification when used as a SHA
calculation unit only. Otherwise, if the ICM is used as integrated check for memory content, the padding is
not mandatory. The SHA module produces an N-bit message digest each time a block is read and a
processing period ends. N is 160 for SHA1, 224 for SHA224, 256 for SHA256.
When the ICM module is enabled, it sequentially retrieves a circular list of region descriptors from the
memory (Main List described in Figure 26-2). Up to four regions may be monitored. Each region
descriptor is composed of four words indicating the layout of the memory region (see also Example in
26.6.3 Region Descriptor Structure). It also contains the hashing engine configuration on a per region
basis. As soon as the descriptor is loaded from the memory and context registers are updated with the
data structure, the hashing operation starts. A programmable number of blocks (see TRSIZE field of the
RCTRL structure member) is transferred from the memory to the SHA engine. When the desired number
of blocks have been transferred, the digest is either moved to memory (Write Back function) or compared
with a digest reference located in the system memory (Compare function). If a digest mismatch occurs,
an interrupt is triggered if unmasked. The ICM module passes through the region descriptor list until the
end of the list marked by an End of List bit set to one. To continuously monitor the list of regions, the
WRAP bit must be set to one in the last data structure.
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 688