Datasheet

Table Of Contents
26.3 Block Diagram
Figure 26-1. Integrity Check Monitor Block Diagram
Integrity
Scheduler
SHA
Hash
Engine
Host
Interface
Context
Registers
Monitoring
FSM
Configuration
Registers
Master
DMA Interface
APB
Bus Layer
26.4 Signal Description
Not applicable.
26.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
26.5.1 Power Management
The ICM will run only when the source clocks are running, i.e. when the CPU is in Active mode.
26.5.2 Clocks
The ICM bus clocks (CLK_ICM_AHB and CLK_ICM_APB) can be enabled and disabled in the Main
Clock module (MCLK) by writing the respective bit in the mask registers (MCLK.AHBMASK.ICM and
MCLK.APBCMASK.ICM).
The default states of CLK_ICM_AHB and CLK_ICM_APB are given by the reset values of the respective
mask registers.
Related Links
15.7 Register Summary
SAM D5x/E5x Family Data Sheet
ICM - Integrity Check Monitor
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 687