Datasheet

Table Of Contents

26. ICM - Integrity Check Monitor

26.1 Overview

The Integrity Check Monitor (ICM) is a DMA controller that performs hash calculation over multiple

memory regions through the use of transfer descriptors located in memory (ICM Descriptor Area). The

Hash function is based on the Secure Hash Algorithm (SHA). The ICM controller integrates two modes of

operation. The first one is used to hash a list of memory regions and save the digests to memory (ICM

Hash Area). The second operation mode is an active monitoring of the memory. In that mode, the hash

function is evaluated and compared to the digest located at a predefined memory address (ICM Hash

Area). If a mismatch occurs, an interrupt is raised.

26.2 Features

• DMA AHB master interface

• Supports monitoring of up to four non-contiguous memory regions

• Supports block gathering through the use of linked list

• Supports Secure Hash Algorithm (SHA1, SHA224, SHA256)

• Compliant with FIPS Publication 180-2

• Configurable processing period:

– When SHA1 algorithm is processed, the run-time period is either 85 or 209 clock cycles.

– When SHA256 or SHA224 algorithm is processed, the run-time period is either 72 or 194 clock

cycles.

• Programmable bus burden

SAM D5x/E5x Family Data Sheet

ICM - Integrity Check Monitor

Datasheet

DS60001507E-page 686