Datasheet

25.8.11 ECC Error Status
Name: ECCERR
Offset: 0x24
Reset: 0x00000000
Property: -
This register tracks errors on the NVM read path.
ECC error tracking is active until an error is detected. It is still active in case of single error but no dual
error. In this case only a dual error can override this register status as a dual error is more critical than a
single error. Error tracking resumes as soon as this register is read.
Bit 31 30 29 28 27 26 25 24
TYPEH[1:0] TYPEL[1:0]
Access
R R R R
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
ADDR[23:16]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ADDR[15:8]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 31:30 – TYPEH[1:0] High Double-Word Error Type
Indicates the type of error detected on the NVM 64-bit most significant read word. It is reset to None
when this register is read except if an error occurs in the same cycle.
Value Name Description
0x0
None No Error Detected Since Last Read
0x1
Single At Least One Single Error Detected Since last Read
0x2
Dual At Least One Dual Error Detected Since Last Read
0x3
Reserved
Bits 29:28 – TYPEL[1:0] Low Double-Word Error Type
Indicates the type of error detected on the NVM 64-bit less significant read word. It is reset to None when
this register is read except if an error occurs in the same cycle.
Value Name Description
0x0
None No Error Detected Since Last Read
0x1
Single At Least One Single Error Detected Since last Read
0x2
Dual At Least One Dual Error Detected Since Last Read
0x3
Reserved
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 680