Datasheet

Bit 5 – ECCDE ECC Dual Error
0: No ECC dual errors have been received since the last ECCERR register read.
1: At least one ECC error has occurred since the last ECCERR register read.
This bit is cleared when the ECCERR register is read.
Bit 4 – ECCSE ECC Single Error
0: No ECC single errors have been received since the last ECCERR register read.
1: At least one ECC error has occurred since the last ECCERR register read.
This bit is cleared when the ECCERR register is read.
Bit 3 – LOCKE Lock Error
0: No LOCK errors have been received since the last clear.
1: At least one LOCK error has occurred since the last clear.
This bit can be cleared by writing a one to its bit location.
Bit 2 – PROGE Programming Error
0: No PROG errors have been received since the last clear.
1: At least one PROG error has occurred since the last clear.
This bit can be cleared by writing a one to its bit location.
Bit 1 – ADDRE Address Error
0: No ADDRE error has been detected since the last clear.
1: At least one ADDRE error has been detected since the last clear.
This bit can be cleared by writing a one to its bit location.
Bit 0 – DONE Command Done
0: The NVM controller has not completed any command since the last clear.
1: At least one command has completed since the last clear.
This bit can be cleared by writing a one to its bit location.
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 674