Datasheet

25.8.5 Interrupt Enable Set
Name: INTENSET
Offset: 0x0E
Reset: 0x0000
Property: PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
SEEWRC SEESOVF SEESFULL
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
SUSP NVME ECCDE ECCSE LOCKE PROGE ADDRE DONE
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 10 – SEEWRC SEE Write Completed Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the SEEWRC interrupt enable.
This bit will read as the current value of the SEEWRC interrupt enable.
Bit 9 – SEESOVF Active SEES Overflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the SEESOVF interrupt enable.
This bit will read as the current value of the SEESOVF interrupt enable.
Bit 8 – SEESFULL Active SEES Full Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the SEESFULL interrupt enable.
This bit will read as the current value of the SEESFULL interrupt enable.
Bit 7 – SUSP Suspended Write Or Erase Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the SUSP interrupt enable.
This bit will read as the current value of the SUSP interrupt enable.
Bit 6 – NVME NVM Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the NVME interrupt enable.
This bit will read as the current value of the NVME interrupt enable.
Bit 5 – ECCDE ECC Dual Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the ECCDE interrupt enable.
This bit will read as the current value of the ECCDE interrupt enable.
Bit 4 – ECCSE ECC Single Error Interrupt Enable
Writing a zero to this bit has no effect.
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 671