Datasheet

Bits 7:6 – PRM[1:0] Power Reduction Mode during Sleep
Indicates the power reduction mode during sleep.
Value Name Description
0x0
SEMIAUTO NVM block enters low-power mode when entering standby mode. NVM block
enters low-power mode when SPRM command is issued. NVM block exits low-
power mode upon first access.
0x1
FULLAUTO NVM block enters low-power mode when entering standby mode. NVM block
enters low-power mode when SPRM command is issued. NVM block exits low-
power mode when system is not in standby mode.
0x2
Reserved
0x3
MANUAL NVM block does not enter low-power mode when entering standby mode. NVM
block enters low-power mode when SPRM command is issued. NVM block
exits low-power mode upon first access.
Bits 5:4 – WMODE[1:0] Write Mode
Write commands can be generated automatically when crossing address boundaries while writing to the
NVM. Boundaries depend on the settings below.
Value Name Description
0x0
MAN Manual Write
0x1
ADW Automatic Double Word Write
0x2
AQW Automatic Quad Word
0x3
AP Automatic Page Write
Bit 3 – SUSPEN Suspend Enable
0: The write and erase suspend resume feature is disabled.
1: A write or erase operation can be suspended in case of a read in the same bank.
Bit 2 – AUTOWS Auto Wait State Enable
0: Automatic wait state generation is disabled. The number of wait states used is given by RWS.
1: Automatic wait state generation is enabled. The number of wait states used is automatically detected
therefore the module can operate at any frequency up to the device maximum frequency. A minimum of
one cycle latency is induced.
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 665