Datasheet

25.8.1 Control A
Name: CTRLA
Offset: 0x0
Reset: 0x0004
Property: PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
CACHEDIS1 CACHEDIS0 AHBNS1 AHBNS0 RWS[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PRM[1:0] WMODE[1:0] SUSPEN AUTOWS
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 1
Bit 15 – CACHEDIS1 AHB1 Cache Disable
AHB1 interface cache disable.
0: cache line is enabled
1: cache line is disabled
Cache lines are automatically invalidated when a write or erase operation is started in the NVM.
Bit 14 – CACHEDIS0 AHB0 Cache Disable
AHB0 interface cache disable.
0: cache line is enabled
1: cache line is disabled
Cache lines are automatically invalidated when a write or erase operation is started in the NVM.
Bit 13 – AHBNS1 Force AHB1 access to Non-Sequential
This bit forces AHB1 communication to be non-sequential.
Value Description
0
AHB sequential accesses remain sequential.
1
AHB sequential accesses are forced to non-sequential, therefore forcing rearbitration for
each access.
Bit 12 – AHBNS0 Force AHB0 access to Non-Sequential
This bit forces AHB0 communication to be non-sequential.
Value Description
0
AHB sequential accesses remain sequential.
1
AHB sequential accesses are forced to non-sequential, therefore forcing rearbitration for
each access.
Bits 11:8 – RWS[3:0] NVM Read Wait States
These bits give the number of wait states for a read operation when AUTOWS=0. Zero indicates zero
wait states, one indicates one wait state, etc., up to 15 wait states.
This register is initialized to 0 wait states. Software can change this value based on the NVM access time
and system frequency.
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 664