Datasheet

ECCERR.TYPEL and ECCERR.TYPEH are reset to the NONE value when ECCERR is read. If an error
occurs while reading ECCERR, the previous error information is sent to the APB and ECCERR is
updated with the next error information.
If a single-error has been detected and INTFLAG.ECCSE or INTFLAG.ECCDE is not clear:
• Any incoming single-errors is ignored
• First incoming dual-error overrides ECCERR.ADDR, ECCERR.TYPEL and ECCERR.TYPEH
If a dual-error has been detected and INTFLAG.ECCDE is not clear:
• incoming single-errors are ignored
• incoming dual-errors are ignored
ECCERR.ADDR is always quad-word aligned. If jumping to a word that is not quad-word aligned, e.g.
jumping to address 0x100C, INTFLAG.ECCDE and INTFLAG.ECCSE are updated according to the types
of detected errors, and ECCERR.ADDR will read 0x1000, irrespective of whether the ECC error was in
address 0x1000, 0x1004, 0x1008, or 0x100C.
25.6.13 Reset During Operation
Program or erase operations must not be interrupted. The content of a block or a page is unpredictable in
case of reset during either an erase or a write operation. To reduce the risk of having a BOD reset due to
a power loss one can monitor the external voltage before issuing any program or erase operation. The
user can also prefer the WQW command instead of the WP command as a short command is more likely
to complete successfully than a long one with a given external decoupling capacitor. In case of reset
during a write or erase operation the impacted block must be erased before being read or programmed
as its content is unknown.
25.6.14 Chip Erase
The Chip Erase operation is system-wide, and issued through the DSU.
Chip-Erase procedure:
1. Volatile memories are cleared and NVM array is erased simultaneously (except the BOOTPROT
section)
2. Special individual fuses are set as follow:
– If no BOOTPROT section is defined then NVMCTRL STATUS.AFIRST=1 otherwise it is left
unchanged
– NVMCTRL SEESTAT.ASEES=1
– NVMCTRL SEESTAT.LOCK=0
– DSU STATUSB.CELCK=0
3. Security bit is cleared provided no internal error has been detected in the previous steps
– If all internal NVM verify operations succeeded: goto 4
– otherwise set DSU.STATUSA.DONE and DSU.STATUSA.FAIL and exit.
4. DSU STATUSB.PROT is cleared, system is no more protected
Note: CB, FS, USER pages (in the auxiliary address space) and the section allocated as a boot loader
using BOOTPROT are not affected by the Chip-Erase operation.
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 661