Datasheet

25.6.12.1 Block Diagram
Figure 25-2. ECC Diagram
NVM Block
ECC
calculation
64
8
64
8
PBLDATA[63:0]
HADDR
ECCERR.ADDR
ECC logic
64
ECCERR.TYPEH
64
8
ECC logic
64
144
INTFLAG.ECCERR INTFLAG.ECCERR
ECCERR.TYPEL
MATRIX
CACHE LINE AHB0
CACHE LINE AHB1
SmartEEPROM
128
128
32
32
Note that the ECC correction is disabled when access is performed by the SmartEEPROM interface.
25.6.12.2 ECC Error Detection
The NVM physical block fetches 128-bit quad-word and ECC checking is performed on a 64-bit basis
independently on the low and high double-words. Therefore two ECC decoders operate in parallel. An
ECC failure may be present in any of the four words from the NVM, not necessarily the word that is
addressed on the bus. Any ECC error in a double-word will be reported the first time the quad-word
access. The ECC logic in the read data path is capable of double error detection and single error
correction on the fly per 64-bit double-word.
Upon detection:
• INTFLAG ECC error flags are updated:
– The ECC single error interrupt flag is raised (INTFLAG.ECCSE) in case of single error
– The ECC dual error interrupt flag is raised (INTFLAG.ECCDE) in case of dual error
• ECCERR.ADDR is updated with the faulty quad-word byte address in the main address space.
• ECCERR.TYPEL is updated with the error type (NONE, SINGLE, DUAL) detected on the low 64-bit
double word.
• ECCERR.TYPEH is updated with the error type (NONE, SINGLE, DUAL) detected on the high 64-bit
double word.
INTFLAG.ECCSE and INTFLAG.ECCDE are automatically cleared when ECCERR is read.
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 660