Datasheet

25.6.10 Security Bit
The security bit allows the entire chip to be locked from external access for code security.
Related Links
12. DSU - Device Service Unit
25.6.10.1 Security Bit Set Procedure
1. Issue the Set Security Bit command (SSB)
This command changes the NVM security bits. The device shadow registers are not changed at
that point. If a debugger was connected, it will still have access to the device after issuing this
command (DSU.STATUSB.PROT will still read ‘0’).
2. Check NVMNCTRL.INTFLAG.PROGE and NVMNCTRL.INTFLAG.DONE.
3. Reset the NVMCTRL peripheral or the device.
To reflect the NVM security bits’ state correctly, the NVMCTRL needs to replay the start-up procedure.
This is done by issuing a SWRST command or by resetting the device.
Related Links
12. DSU - Device Service Unit
25.6.10.2 Security Bit Clear Procedure
The only way to clear the security bit is through a debugger Chip Erase command. The NVM security bit
is cleared after all internal volatile and NVM have been cleared. The device protection status is updated
at the end of the command meaning that no reset is necessary.
Related Links
12. DSU - Device Service Unit
25.6.11 Line Cache
NVM reads 128-bit at a time. AHB0 and AHB1 interfaces implement each a 128-bit cache line.This
reduces the device power consumption when reading continuous data and improves system performance
when wait states are required. Line cache are enabled by default and can be individually disabled per
AHB interface by writing a one in the CACHEDIS[0] or CACHEDIS[1] bit in the CTRLA register
(CTRLA.CACHEDIS[1:0]). Refer to CTRLA register description for more details. Commands affecting
NVM content automatically invalidate cache lines.
25.6.12 Error Correction Code (ECC)
Error Correcting Code (ECC) is implemented to detect and correct errors that may arise in the NVM array.
ECC is by default enabled and cannot be disabled by the user.
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 659