Datasheet

...........continued
SEESTAT
.PSZ:
SEESTAT
.SBLK
4 8 16 32 64 128 256 512
5 16 16 16 16 16 16 16 11
6 16 16 16 16 16 16 16 27
7 16 16 16 16 16 16 16 43
8 16 16 16 16 16 16 16 59
9 16 16 16 16 16 16 16 11
10 16 16 16 16 16 16 16 16
25.6.9 NVM User Configuration
The NVM user configuration resides in the auxiliary space. Refer to the Physical Memory Map and
Product Mapping of the device for calibration and auxiliary space address mapping.
The NVM user configuration is:
• The boot loader size. The bootloader resides in the main array starting at offset zero. The allocated
boot loader section is protected against erase or write operations including the chip erase operation.
• The SmartEEPROM number of blocks per SEES (SBLK bits). This configuration is loaded after a
reset into SEESTAT.SBLK bits.
• The SmartEEPROM virtual page size (PSZ bits). This configuration is loaded after a reset into
SEESTAT.PSZ bits.
• The region lock bits (reflected in the RUNLOCK register)
• The SmartEEPROM RUNLOCK bit (reflected in SEESTAT.LOCK)
Table 25-10. Boot Loader Size
BOOTPROT [3:0] Rows Protected by BOOTPROT Boot Loader Size in KBytes
15 None 0
14 1 8
13 2 16
12 3 24
11 4 32
10 5 40
9 6 48
8 7 56
7 8 64
6 9 72
5 10 80
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 657