Datasheet

on the SEESTAT.PSZ and SEESTAT.SBLK user configuration. As there are two SEES the wear leveling is
two times the maximum SEEP number.
Table 25-8. Wear leveling depending on SEESTAT.PSZ and SEESTAT.SBLK
SEESTAT
.PSZ:
SEESTAT
.SBLK
4 8 16 32 64 128 256 512
0 N/A N/A N/A N/A N/A N/A N/A N/A
1 288 288 288 288 190 94 46 22
2 288 288 288 288 288 222 110 54
3 288 288 288 288 288 288 174 86
4 288 288 288 288 288 288 238 118
5 288 288 288 288 288 288 238 150
6 288 288 288 288 288 288 238 182
7 288 288 288 288 288 288 238 214
8 288 288 288 288 288 288 238 246
9 288 288 288 288 288 288 238 278
10 288 288 288 288 288 288 238 288
25.6.8.6 Writing and Reading the SmartEEPROM
SEESTAT.LOCK must be ‘0’; otherwise, writes are discarded and a hardfault exception is thrown.
SmartEEPROM write access can be locked with the LSEE command and unlocked with the USEE
command.
1. Configure SBLK and PSZ fuses to define the SmartEEPROM total size and size of each page.
2. Define a pointer to the SmartEEPROM area. It can be used for 8-, 16- or 32-bit access.
volatile uint8_t *SmartEEPROM8 = (uint8_t *) SEEPROM_ADDR; volatile uint16_t
*SmartEEPROM16 = (uint16_t *) SEEPROM_ADDR; volatile uint32_t *SmartEEPROM32 = (uint32_t
*) SEEPROM_ADDR;
3. Wait until SmartEEPROM is busy.
while (NVMCTRL->SEESTAT.bit.BUSY);
4. Write to the EEPROM like writing a RAM location. Perform an 8-, 16- or 32-bit write.
5. If automatic reallocation is disabled with SEECFG.APRDIS, check the SEESFULL interrupt flag to
ensure that the active SmartEEPROM sector is not full.
6. To read back the content, read the location using the defined pointer.
uint8_t eep_data_8 = 0; while (NVMCTRL->SEESTAT.bit.BUSY); eep_data_8 = SmartEEPROM8[0];
There are two NVM pagebuffer management modes available, selected by writing the SEECFG.WMODE
bit field:
• UNBUFFERED (default): WP command triggered after any pagebuffer update
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 655