Datasheet

Table 25-6. SmartEEPROM Virtual Size in Bytes
SEESTAT.PSZ: SEESTAT.SBLK 4 8 16 32 64 128 256 512
0 0 0 0 0 0 0 0 0
1 512 1024 2048 4096 4096 4096 4096 4096
2 512 1024 2048 4096 8192 8192 8192 8192
3 512 1024 2048 4096 8192 16384 16384 16384
4 512 1024 2048 4096 8192 16384 16384 16384
5 512 1024 2048 4096 8192 16384 32768 32768
6 512 1024 2048 4096 8192 16384 32768 32768
7 512 1024 2048 4096 8192 16384 32768 32768
8 512 1024 2048 4096 8192 16384 32768 32768
9 512 1024 2048 4096 8192 16384 32768 65536
10 512 1024 2048 4096 8192 16384 32768 65536
• The italic cells indicate sub-optimal configurations, unnecessary blocks are allocated.
• The bold cells indicate optimal valid configurations with the maximum number of SEEP depending
on SEESTAT.PSZ and SEESTAT.SBLK (see the table below).
• Other cells indicate valid configurations with the maximum number of SEEP depending on
SEESTAT.PSZ and SEESTAT.SBLK.
Table 25-7. Maximum Number of SEEP depending on SEESTAT.PSZ and SEESTAT.SBLK
SEESTAT.PSZ: SEESTAT.SBLK 4 8 16 32 64 128 256 512
0 N/A N/A N/A N/A N/A N/A N/A N/A
1 144 144 144 144 95 47 23 11
2 144 144 144 144 144 111 55 27
3 144 144 144 144 144 144 87 43
4 144 144 144 144 144 144 119 59
5 144 144 144 144 144 144 144 75
6 144 144 144 144 144 144 144 91
7 144 144 144 144 144 144 144 107
8 144 144 144 144 144 144 144 123
9 144 144 144 144 144 144 144 139
10 144 144 144 144 144 144 144 144
25.6.8.5 SmartEEPROM wear leveling
The wear leveling factor is the minimum ratio per which the access frequency to a physical flash cell is
divided when the maximum number of SEEP in a SEES is reached. This maximum number is depends
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 654