Datasheet

25.6.7 Safe Flash Update Using Dual Banks
This feature enables a firmware to execute from the NVM and at the same time program the Flash with a
new version of itself.
The new firmware has to be programmed in BANKB if STATUS.AFIRST=1, or BANKA otherwise.
After programming is completed one can issue the BKSWRST command to swap the banks and to reset
the device. The information of which BANK is mapped to the NVM main address space base address is
self contained in the NVM using a special fuse that can be programmed or erased individually. This fuse
is managed by the BKSWRST command. STATUS.AFIRST reflects the status of this fuse after Reset.
The BKSWRST command is atomic meaning that no fetch in the NVM can occur while executing this
command. This command executes with the following steps:
1. Stall AHB interfaces.
2. If PARAM.SEE is ‘1’ and 0<SEESTAT.SBLK<11, the NVMCTRL starts to reallocate the
SmartEEPROM data to the first bank. Active SEES remains the same at the end of the reallocation.
3. Is STATUS.AFIRST=1: program the AFIRST fuse (new value=0) otherwise erase it (new value=1)
4. Resets the device, After reset, RSTC RCAUSE indicates that the reset was triggered by the
NVMCTRL.
After Reset the new firmware is executed from the last programmed bank.
If the SmartEEPROM is configured, the size of the the reserved space in flash must not exceed the bank
size. In other words 2*SEESTAT.SBLK.8192 must be lower than half the NVM size in Bytes. In situations
where both the banks contain separate applications (or an application in one bank and a bootloader in the
other bank), both the banks must have Flash area reserved for SmartEEPROM. This means that the
usable area for code in each bank is "Size of the Bank", that is, the size of the Flash configured for the
SmartEEPROM using SBLK Fuse.
25.6.8 SmartEEPROM
25.6.8.1 Principle of Operation
The SmartEEPROM feature is provided through the AHB2 interface and makes a portion of the NVM
appear like a RAM. 8-bit, 16-bit, 32-bit access is supported.
The SmartEEPROM concept relies on the following NVM physical property: It is always possible to write a
'0' in a NVM word, even if this word has been previously programmed - but it is not possible to write a '1'
to a bit already programmed (holding a '0').
The algorithm consists of virtually mapping physical portions of the NVM to logical addresses with an
indirection mechanism. A physical page is assigned to a virtual page address and is kept as long as no
bit has to be flipped from '0' to '1', as this operation requires a full block erase. In case such a transition is
required, a new physical page is assigned to the modified virtual page (placed in the Flash area reserved
for the SmartEEPROM). Writing the virtual page affects the cycling endurance of the SmartEEPROM.
A region can overlap the SmartEEPROM region (depending on the allocated space for the
SmartEEPROM), but SmartEEPROM is independent of the Region Lock Bits.
If NVMCTRL.STATUS.AFIRST contains '1', BANKA is mapped to the NVM main address space base
address (0x0000). In this case, SmartEEPROM will be in BANKB. Conversely, when BANKB is mapped
to the NVM main address space base address, SmartEEPROM will be in BANKA. Thus, the CPU is not
halted when accessing the SmartEEPROM.
25.6.8.2 Address Spaces
The SmartEEPROM address space is divided in two distinct areas:
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 652