Datasheet

The block to be written must be erased before the last write to the page buffer is performed. The internal
write operation will begin when the second word is written for WMODE = ADW, when the fourth word is
written for WMODE = AQW, and when the last word of the page is written for WMODE = APW.
Note that partially written pages must be written with a manual write.
If the command interface is already processing a command, the AHB is stalled until the automatic write
command is taken. Therefore it is possible to chain write commands without polling STATUS.READY. For
applications that must not stall the AHB bus the automatic write must be used carefully: STATUS.READY
must be checked after each double-word or quad-word or page buffer write depending on WMODE
before chaining with a new write to avoid stalling the bus.
• Write to the page buffer by addressing the NVM main address space directly.
– When the word location in the page buffer is written, the double word or quad word or page is
automatically written to NVM main address space.
• STATUS.READY will be zero while programming is in progress and access through the AHB will be
stalled.
NVM Write Example (Manual Write mode)
1. Configure manual write for the NVM using WMODE (NVMCTRL.CTRLA).
2. Make sure the NVM is ready to accept a new command (NVMCTRL.STATUS).
3. Clear page buffer ( NVMCTRL.CTRLB).
4. Make sure NVM is ready to accept a new command (NVMCTRL.STATUS).
5. Clear the DONE Flag (NVMCTRL.INTFLAG).
6. Write data to page buffer with 32-bit accesses at the needed address.
7. Perform page write (NVMCTRL.CTRLB).
8. Make sure NVM is ready to accept a new command (NVMCTRL.STATUS).
9. Clear the DONE Flag (NVMCTRL.INTFLAG).
25.6.6.3 Read While Write (RWW)
This feature makes it possible to program and read the NVM simultaneously without stalling the AHB bus
independantly from any cache consideration. The basic principle is that NVM is made of two banks, one
can be read while the other is programmed.
Limitations:
• It is not possible to read both banks simultaneously, reads will be prioritized and issued in series.
• It is not possible to program or erase both banks simultaneously, a new command will be accepted
only after the completion of the previous one, otherwise the new command is ignored and
INTFLAG.PROGE is set.
• RWW is not possible when reading or programming auxilliary pages, any read will result in an AHB
stall and the command interface doesn’t accept any command until completion of the previous one.
25.6.6.4 Suspend/Resume
This feature can be enabled by writing a ‘1’ to CTRLA.SUSPEN. Any modify operation, such as write or
erase can be suspended even those triggered by the SmartEEPROM.
When enabled, the following commands are suspended by a NVM read request:
• EB
• WP
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 649