Datasheet

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WP WQW EP EB
User Page Address
Space
X X
Issuing an unsupported command on an address space sets the PROGE interrupt flag.
After programming the NVM main array, the region that the page resides in can be locked to prevent
spurious write or erase sequences. Locking is performed on a per-region basis, and so locking a region
locks all pages inside the region.
Data to be written to the NVM block is written through AHB and stored in an internal buffer called the
page buffer. If the NVMCTRL is busy processing a write command (STATUS.READY=0) then the AHB
bus is stalled upon an AHB write until the ongoing command completes. Writing the page buffer is
allowed during a block erase operation. The page buffer contains the same number of bytes as an NVM
page. Writes to the page buffer must be 32 bits. 16-bit or 8-bit writes to the page buffer is not allowed,
and will cause a PAC error. Internally, writes to the page buffer are on a 64-bit basis through the page
buffer load data registers (PBLDATA[1] and PBLDATA[0]). The PBLDATA register is a holding register for
writes to the same 64-bit page buffer section. Data within a 64-bit section can be written in any order.
Crossing a 64- bit boundary will reset the PBLDATA register to all ones. The following example assumes
startup from reset where the current address is 0 and PBLDATA is all ones. Only 64 bits of the page
buffer are written at a time, but 128 bits are shown for reference.
Sequential 32-bit write example:
• 32-bit 0x1 written to address 0
– Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, PBLDATA[63:32], 0x00000001}
– PBLDATA[63:0] = {PBLDATA[63:32], 0x00000001}
• 32-bit 0x2 written to address 1
– Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, 0x00000002, PBLDATA[31:0]
– PBLDATA[63:0] = 0x00000002, PBLDATA[31:0]}
• 32-bit 0x3 written to address 2 (crosses 64-bit boundary)
– Page buffer[127:0] = 0xFFFFFFFF_00000003_00000002_00000001
– PBLDATA[63:0] = 0xFFFFFFFF_00000003
Random access writes to 32-bit words within the page buffer will overwrite the opposite word within the
same 64-bit section with ones. In the following example, notice that 0x00000001 is overwritten with
0xFFFFFFFF from the third write due to the 64-bit boundary crossing. Only 64 bits of the page buffer are
written at a time, but 128 bits are shown for reference.
Random access 32-bit AHB write example:
• 32-bit 0x1 written to address 2
– Page buffer[127:0] = 0xFFFFFFFF_00000001_FFFFFFFF_FFFFFFFF
– PBLDATA[63:0] = 0xFFFFFFFF_00000001
• 32-bit 0x2 written to address 1
– Page buffer[127:0] = 0xFFFFFFFF_00000001_00000002_FFFFFFFF
– PBLDATA[63:0] = 0x00000002_FFFFFFFF
• 32-bit 0x3 written to address 3
– Page buffer[127:0] = 0x00000003_FFFFFFFF_00000002_FFFFFFFF
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 647