Datasheet

Table Of Contents

The APB ADDR register is updated upon:

• APB writes to the ADDR register address

• AHB writes to the page buffer

ADDR APB writes are discarded and report an INTFLAG.ADDRE error in the following cases:

• When written from APB while a command is reading it.

• ADDR APB write access while writing the page buffer (AHB write): ADDR is written upon AHB writes

and must stay valid until the page buffer has been written and also until automatic write command

has been issued to the command interface when in automatic write mode (WMODE configured as

ADW or AQW or AP).

• ADDR APB write access while the command interface reads it.

• A command is executed at an illegal address

All commands that require an address are discarded when INTFLAG.ADDRE is set. INTFLAG.PROGE is

set in this case. INTFLAG.ADDRE must be cleared before issuing such commands.

25.6.6.1 NVM Read

Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main

address space or auxiliary address space directly. Read data is available after the number of read wait

states has passed as configured in NVMCTRL.CTRLA.RWS.

The number of cycles data are delayed to the AHB bus is determined by the read wait states.

It is not possible to read two banks at the same time. In case of simultaneous read operations,

transactions are arbitrated by the internal matrix. Arbitration scheme is fixed priority, AHB0 has the

highest priority, AHB1 has priority over AHB2. In case of conflict, AHB interfaces with lower priority are

stalled.

Reading in a bank stalls the bus when it is being programmed or erased except when the suspend

feature is used.

Reading in a bank does not stall the bus when the other bank is being programmed or erased.