Datasheet

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10.3 High-Speed Bus System
25.6.5 Region Lock Bits
The NVM main address space is accessible through the AHB0 or AHB1 interfaces, and grouped into 32
equally sized regions regardless of BOOTPROT or SmartEEPROM settings. The region size is
dependent on the flash memory size, and is given in the table below. Each region has a dedicated lock bit
preventing writing and erasing pages in the region. After production, all regions will be unlocked.
Table 25-4. Region Size
Memory Size [KB] Region Size [KB]
1024 32
512 16
256 8
To lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of
these commands will temporarily lock/unlock the region containing the address loaded in the ADDR
register. ADDR can be written by software, or the automatically loaded value from a AHB write operation
can be used. The new setting will stay in effect until the next reset, or the setting can be changed again
using the lock and unlock commands. The current status of the lock can be determined by reading the
RUNLOCK register.
To change the default lock/unlock setting for a region, the user page must be written. Writing to the
auxiliary space will take effect after the next reset. Therefore, a boot of the device is needed for changes
in the lock/unlock setting to take effect. Refer to the Physical Memory Map for calibration and auxiliary
space address mapping.
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9.2 Physical Memory Map
25.6.6 Command and Data Interface
The NVM Controller is addressable from the APB bus, while the NVM main address space is addressable
from the AHB bus. Read and automatic page write operations are performed by addressing the NVM
main address space directly, while other operations such as manual page writes and block erase must be
performed by issuing commands through the NVM Controller.
To issue a command, the CTRLB.CMD bits must be written along with the CTRLB.CMDEX value.
STATUS.READY is cleared when a command is issued and set when it has completed. Any command
written while STATUS.READY is low will be ignored causing INTFLAG.PROGE to rise. Refer to CTRLB
register description for more details.
Invalid commands are discarded and will set INTFLAG.PROGE and INTFLAG.DONE when issued.
The CTRLA register must be used to control the power reduction mode, read wait states and the write
mode.
Commands that require an address use the ADDR register as an argument. ADDR APB write access is
locked by the NVMCTRL while being used internally. For instance if a write operation is started by the
NVMCTRL, an APB write is discarded so that the write operation is performed at the correct address. The
discarded APB write is signaled by rising INTFLAG.ADDRE. Commands that needs an address will fail if
issued while INTFLAG.ADDRE is set, such failure is signaled by rising INTFLAG.PROGE.
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 645