Datasheet

hardfault exception. Any command issued with ADDR pointing in the SmartEEPPROM space is
discarded, INTFLAG.DONE and INTFLAG.ADDRE are set in this case.
– Address: PARAM.NVMP*512-2*SEESTAT.SBLK*8192
– Size: 2*SEESTAT.SBLK*8192
– Property: Not readable, not writeable
Each section has different protection status, refer to the table below.
Table 25-3. Protection status
Section/Operation Write protection Erase protection Chip-Erase protection
Bootloader Yes Yes Yes
SmartEEPROM Configurable Configurable No
Main Array Configurable Configurable No
Related Links
9.2 Physical Memory Map
12. DSU - Device Service Unit
25.6.3 Memory Bank Swapping
The two physical banks BANKA and BANKB are mapped in the NVM main address space and can be
swapped. If STATUS.AFIRST contains '1', then BANKA is mapped to the NVM main address space Base
Address, otherwise it is BANKB.
The start address of BANKA & BANKB depends on STATUS.AFIRST and on the size of the Flash. Refer
to the Physical Memory Map for memory sizes and addresses for each device.
Related Links
9.2 Physical Memory Map
25.6.4 AHBMUX Arbitration
The AHBMUX arbitrates concurrent AHB0, AHB1 and SmartEEPROM accesses using a fixed priority
scheme:
• AHB0 has the highest priority
• AHB1 has priority over SmartEEPROM
• AHB2 has the lowest priority
However, once a transfer has been accepted the AHB data phase must complete, meaning that a
transaction can be stalled by a previously granted access with a lower priority. This can occur in
Automatic Wait State mode or in Fixed Wait State mode when the Wait state is greater than zero.
AHBMUX doesn’t rearbitrate AHB burst transactions. This is useful in case of concurrent write transfers to
the page buffer. If used in conjunction with the automatic write features (ADW, AQW, APW) and if the
burst transfer size is a multiple of the automatic write size, several masters can write the NVM without
implementing any software semaphore checks.
It is possible to force the rearbitration in case of burst transfers, as follows:
• on AHB0: by writing a ‘1’ to CTRLA.AHBNS0
• on AHB1: by writing a ‘1’ to CTRLA.AHBNS1
SAM D5x/E5x Family Data Sheet
NVMCTRL – Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 644